DON26BZ01-NV024 TITLE: 3D-Heterogeneously Integrated Photonic (HIP) Imaging Sensor

OUSW (R&E) CRITICAL TECHNOLOGY AREA(S): Quantum and Battlefield Information Dominance (Q-BID)

COMPONENT TECHNOLOGY PRIORITY AREA(S): Advanced Materials;Integrated Sensing and Cyber;Microelectronics

PROJECTED CMMC LEVEL REQUIREMENT: Level 2 (Self)

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws.

OBJECTIVE: Design, fabricate, and verify the performance of a 3D-heterogeneously integrated photonic (HIP) imaging sensor consisting of a detector array, read-out integrated circuit (ROIC), and photonic transmitter.

DESCRIPTION: Emerging military electro-optical and infrared (EO/IR) sensors enable high resolution through small pixels, wide field-of-view through large arrays, and high frame rate through high sensitivity and low latency. For the most advanced focal plane array (FPA) sensors, the data bandwidth dictated by the high pixel count and bit rate is reaching the limits of conventional copper wire interconnects. Datalinks using optical interconnects offer a unique and commercially mature solution that can obviate the copper bandwidth limitation, while offering additional advantages of lower power, lower cost, and on-chip integration. For large arrays, the high data rate can be further managed by tiling synchronized, independently addressed smaller arrays, which divides the serialized data stream into multiple parallel paths, while also improving foundry yield. However, existing FPA layouts place read-out electronics, including column analog-to-digital converters, serializers, and bias sources, along the periphery of the imaging chip. To enable tiling with sub-pixel gaps between tiles, the peripheral electronics must be moved below the detector layer. A photonic layer could also be added to create a 3D vertically integrated FPA stack, enabling large arrays to operate at exceptionally high data rates. 3D heterogeneous integration of the FPA stack can be accomplished using bump-bonding, direct-bond integration, or other techniques, but ultra-low capacitance connections are required for low-noise operation to permit the short photon integration times inherent to high-frame-rate imaging. As militarily relevant EO-IR imagers often operate at cold temperatures of 100K+/-20K, the 3D HIP FPA transmitter must also perform well under cryogenic conditions. When tiled in large arrays of small pixels, the 3D-HIP imaging sensor will provide concurrent wide-FOV, high-resolution, and ultra-high frame rate, circumventing conventional imaging sensor paradigms. Frame rate should use 1 KHz as the goal is to address high data rate challenges, however, since the pixel size and format are flexible for this effort, this is not a hard requirement. This SBIR topic’s intent is the development and maturation of 3D heterogeneous integration (3DHI) of electrical and optical/photonic layers that achieves high bandwidth interconnection.

PHASE I: Perform a trade study of design variables. Create a concept for a 3D-HIP imaging sensor design. All design features must be supported by quantitative modelling, simulations, or general trade analysis. The design should be adaptable to all EO/IR spectral bands, formats, and pixel sizes. Address detector, ROIC, and photonic layer designs and interconnections. Within the photonic layer, the laser type and location (inside vs outside the cold space), the optical modulation scheme, optical and electronic bandwidth and compatibility, and energy efficiency must be addressed. The proposed design must include a detailed noise analysis, including component capacitance projections and variances, along with other noise sources. A full link analysis must be provided, including both energy efficiency and data bandwidth. Prepare a Phase II plan that includes the fabrication, integration, and testing strategy.

PHASE II: Fabricate a prototype 3D-HIP imaging sensor based on the Phase I design. It is expected, but not required, that detector, electronic, and photonic layers will be fabricated and integrated at separate foundries, potentially using different foundry nodes. While only a 3D-HIP transmitter is required, the output must be received and processed into imagery. Fabrication of a symmetrically designed transmitter and receiver pair is encouraged. Moreover, the transmitter chip should be compatible with formation of a tiled array. The transmitter-to-receiver connection should employ optical fiber of nominally 1 meter length. The transceiver performance will be thoroughly documented in the Phase II final report.

PHASE III DUAL USE APPLICATIONS: Support the transition to Navy use. High-resolution, wide-FOV, high-speed imagers will find wide use in many commercial and industrial applications such as computer vision, autonomous navigation, security and industrial facility surveillance monitoring.

REFERENCES:

1. Daudlin, S. et al., "Three-dimensional photonic integration for ultra-low-energy, high-bandwidth interchip data links." Nature Photonics 19, 2025, pp. 502-509,. https://www.nature.com/articles/s41566-025-01633-0
2. Liu, Y. et al. "A Novel 16-Channel WDM Silicon Photonics Transceiver with Interleaves for Simplified Ring Modulator/Filter Implementation." Conference on Lasers and Electro-Optics (CLEO), 2022. https://opg.optica.org/abstract.cfm?uri=CLEO_SI-2022-STh4K.3
3. Miller, D. A. B. "Energy consumption in optical modulators for interconnects." Opt. Express 20, A2012, pp. 293–A308. https://opg.optica.org/oe/abstract.cfm?uri=oe-20-s2-a293
4. Georgas, M.; Leu, J.; Moss, B.; Sun, C. and Stojanovic, V., "Addressing link-level design tradeoffs for integrated photonic interconnects." 2011 IEEE Custom Integrated Circuits Conference (IEEE), 2011, pp. 1-8. https://ieeexplore.ieee.org/document/6055363

KEYWORDS: Sensors, read-out integrated circuit, ROIC, photonics, tiling, chiplet, heterogeneous integration

TPOC 1
Richard Espinola
richard.l.espinola.civ@us.navy.mil

TPOC 2
Myron Pauli
myron.r.pauli.civ@us.navy.mil