DON27BZ02-NV011 TITLE: Low-cost Mid-wave Infrared Focal-Plane Array (FPA) Fabrication through Direct-bond Interconnection

OUSW (R&E) CRITICAL TECHNOLOGY AREA(S): Quantum and Battlefield Information Dominance (Q-BID)

COMPONENT TECHNOLOGY PRIORITY AREA(S): Integrated Sensing and Cyber;Microelectronics

PROJECTED CMMC LEVEL REQUIREMENT: Level 2 (Self)

The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), 22 CFR Parts 120-130, which controls the export and import of defense-related material and services, including export of sensitive technical data, or the Export Administration Regulation (EAR), 15 CFR Parts 730-774, which controls dual use items. Offerors must disclose any proposed use of foreign nationals (FNs), their country(ies) of origin, the type of visa or work permit possessed, and the statement of work (SOW) tasks intended for accomplishment by the FN(s) in accordance with the Announcement. Offerors are advised foreign nationals proposed to perform on this topic may be restricted due to the technical data under US Export Control Laws. 

OBJECTIVE: Develop a focal-plane array (FPA) fabrication process based on wafer-scale 3D-heterogeneous integration that enables a mid-wave infrared (MWIR) III-V detector epi-layer wafer to be directly bonded to a Silicon-based read-out integrated circuit (Si-ROIC) wafer, thereby eliminating the inefficient die-level Indium (In) bump-bonding process currently required to assemble Mid-wave Infrared (MWIR) FPA sensor chips.

DESCRIPTION: Electro-Optic and Infrared (EO/IR) sensors are used in a wide variety of applications, such as navigation, wide-area surveillance, and targeting. Operating in the visible and near-IR bands, EO sensors are available with small pixels and in large arrays at low cost, because the Si-detector wafer and Si-ROIC wafer can be 3D-integrated directly through wafer-to-wafer bonding with high yield at high volume based on material and complementary metal-oxide-semiconductor (CMOS)-process compatibility. By contrast, sensors operating in the MWIR employ III-V detector materials, which are not CMOS-process compatible, while III-V epi-layer detectors cannot be epitaxially grown directly on Si, as required to produce the crystalline order of high-quality detectors [Refs 1-2]. Instead, the III-V detector epi-layer is grown on a lattice-compatible substrate wafer, which is then flip-chip bonded to a Si-ROIC through a dense array of sub-pixel indium bumps placed on each wafer, followed by detector-substrate removal. The technically demanding process of depositing, aligning, and compressing the dense arrays of indium bumps on detector and ROIC die, results in a labor-intensive, inefficient, low-yield process for IR FPA fabrication, which greatly increases cost.

In recent years, 3D-heterogeneous integration has enabled a single integrated chip of greater overall functionality to be realized at reduced cost by assembling multiple smaller chips, each having unique functionality, material, node size, and/or foundry origin. Direct-bond interconnection (DBI) [Refs 3-5] is a 3D-heterogeneous integration technique that can potentially enable low-cost MWIR FPA fabrication. In principle, DBI should enable very large format FPAs with small pixels to be fabricated, as the process is largely independent of wafer and pixel size, in contrast to conventional bump-bonding. Moreover, the DBI process utilizes a temperature range that is compatible with MWIR IR detector materials.

The goal of this SBIR topic is to demonstrate the use of DBI or a similar process for fabrication of high-performance, large format, small-pixel, MWIR FPAs at low cost with the objective of refining the technique sufficiently to potentially replace conventional bump-bonding.

PHASE I: Plan a detailed concept for a FPA fabrication and characterization process, including a risk assessment. While the pixel unit cell design is flexible, a pixel size of less than or equal to 10 micro-meters (um) and format of at least 2K x 2K are required, but otherwise any existing or commercially available Si-based ROIC can potentially be used for this effort. The III-V detector epi-layer spectral response must cover at least the MWIR band (3-5 um). The specific foundry and fabrication process steps will be determined in Phase I. Develop a detailed FPA characterization plan, including measurement of inter-wafer voids, pixel operability, and yield. Perform a per-FPA cost analysis that compares DBI or the selected alternative process to conventional bump-bonding and includes an assessment of the cost impact of process selection trade-offs.

PHASE II: Use the DBI or selected alternative process to fabricate multiple wafers of FPAs having less or equal to 10 um pixels and greater than or equal to 2K x 2K format. Dice and thoroughly characterize the FPAs. Integrate one or more FPA sensor chips into an imaging system and subsequent optical performance characterization (favorable but is not required under this effort.) Prepare a Phase III commercialization/transition plan.

PHASE III DUAL USE APPLICATIONS: Build and test an imaging sensor employing a DBI-fabricated FPA with available Phase III funding upon successful completion of Phase II.

The advancement of MWIR imagers could support many dual-use applications, such as border security, law enforcement, and industrial process monitoring. In general, the advancement of 3D-HI and DBI specifically could facilitate the development of novel micro-electronic devices beyond MWIR imagers.

REFERENCES:

1. Rogalski, A. "Recent progress in infrared detector technologies." Infrared Physics & Technology, 54(3), 2011, pp. 136-154. https://www.scirp.org/reference/referencepapers?referenceid=838480
2. Martyniuk, P. and Rogalski, A. "HOT infrared photodetectors." Opto-Electronics Review, 21(2), 2013, pp. 239-257. https://www.researchgate.net/publication/257909096_HOT_infrared_photodetectors
3. US Patent 9,082,627: Method for low temperature bonding and bonded structure (covers the core process of room or low-temperature dielectric-to-dielectric and metal-to-metal bonding). https://patents.google.com/patent/US9082627B2/zh
4. US Patent 6,962,835: Method for room temperature metal direct bonding. https://patents.google.com/patent/US6962835B2
5. US Patent 9,391,143: Method for low temperature bonding and bonded structure. https://patents.google.com/patent/US9391143B2

KEYWORDS: Focal plane array, FPA, direct-bond interconnection, DBI, 3D heterogeneous integration, 3D HI, infrared imaging, IR, semiconductor processing, read out integrated circuit, ROIC, sensor chip assembly, SCA, mid-wave infrared, MWIR, IR detector materials

TPOC 1: Richard Espinola
richard.l.espinola.civ@us.navy.mil

TPOC 2: Myron Pauli
myron.r.pauli.civ@us.navy.mil